International Journal of Advanced Engineering Application

Low-Power FinFET 7nm VLSI Design for High-Speed SerDes Applications with PVT Variability Analysis and SRAM Static Noise Margin Optimisation

Author(s):Sven Hollemann

Affiliation: Institute of Microelectronics, Fraunhofer Institute for Integrated Circuits (IIS), Erlangen, Germany

Page No: 79-82

Volume issue & Publishing Year: Volume 3, Issue 4, 2026/04/14

Journal: International Journal of Advanced Engineering Application (IJAEA)

ISSN NO: 3048-6807

DOI: https://doi.org/10.5281/zenodo.19703422

Download PDF Cite this article

Article Indexing:

Abstract:
India's semiconductor ambitions, crystallised in the ₹76,000 crore Semiconductor Mission launched in 2022 and accelerated by the approval of three fabrication and ATMP facilities in 2024 — including Tata Electronics' 28nm facility in Dholera and Micron Technology's ATMP unit in Sanand — are driving unprecedented demand for domestic VLSI design talent and research capability. The transition from 28nm planar CMOS to 7nm FinFET technology, now the dominant node for high-performance mobile and edge AI processors manufactured globally, introduces fundamentally different device physics, power management strategies, and circuit design methodologies that Indian academic institutions and fabless IC design companies must master to compete in the global semiconductor supply chain. This paper presents a comprehensive low-power design study for a 10 Gbps Serialiser-Deserialiser (SerDes) transmitter implemented in 7nm FinFET technology using a commercial PDK, comparing power, energy-delay product, leakage, and signal integrity against a 28nm bulk CMOS reference design. The study evaluates dynamic power scaling through supply voltage reduction (0.6-0.9V VDD), multi-threshold voltage (Vt) cell library optimisation, clock gating efficiency, and body bias tuning. Complementary SRAM 6T bit cell analysis establishes the static noise margin versus supply voltage relationship that determines the minimum operating voltage (VMIN) for the on-chip cache. Process-Voltage-Temperature (PVT) corner analysis quantifies the parametric variability that constrains timing closure. The Fraunhofer IIS collaboration provides the 7nm SPICE model parameters calibrated from silicon measurements that ground the simulation results in physical measurement data.

Keywords: FinFET, VLSI, low power, 7nm, CMOS, SerDes, SRAM, SNM, PVT corners, EDP, leakage, semiconductor, India, SPICE

Reference:

• [1] Auth, C., et al. (2012). A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors. IEEE Symposium on VLSI Technology, 131-132.
• [2] Frank, D. J., et al. (2001). Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, 89(3), 259-288.
• [3] Hollemann, S., & Kuesters, K. H. (2022). FinFET device modelling for 7nm VLSI design. IEEE Transactions on Electron Devices, 69(6), 3112-3124.
• [4] Krishnamurthy, M., & Lakshmi, D. (2023). Low power SerDes design in 7nm FinFET. VLSI Design Journal, 36(4), 412-428.
• [5] Liu, T. J. K., & Kuhn, K. (Eds.). (2013). CMOS and Beyond: Logic Switches for Terascale Integrated Circuits. Cambridge University Press.
• [6] Stillmaker, A., & Baas, B. (2017). Scaling equations for the accurate prediction of CMOS device performance. IEEE Design & Test, 34(3), 26-33.
• [7] Tsai, M. H., et al. (2020). Advanced FinFET and GAA nanosheet transistors. IEEE International Electron Devices Meeting, 7.1.1-7.1.4.
• [8] Weste, N. H. E., & Harris, D. M. (2015). CMOS VLSI Design: A Circuits and Systems Perspective (4th ed.). Pearson.