Cite this article

Low-Power FinFET 7nm VLSI Design for High-Speed SerDes Applications with PVT Variability Analysis and SRAM Static Noise Margin Optimisation
https://www.ijaea.com/papers?paper=Low-Power+FinFET+7nm+VLSI+Design+for+High-Speed+SerDes+Applications+with+PVT+Variability+Analysis+and+SRAM+Static+Noise+Margin+Optimisation

Sven Hollemann. (2026). Low-Power FinFET 7nm VLSI Design for High-Speed SerDes Applications with PVT Variability Analysis and SRAM Static Noise Margin Optimisation. International Journal of Advanced Engineering Application (IJAEA), 79-82. https://doi.org/10.5281/zenodo.19703422

Sven Hollemann. "Low-Power FinFET 7nm VLSI Design for High-Speed SerDes Applications with PVT Variability Analysis and SRAM Static Noise Margin Optimisation." International Journal of Advanced Engineering Application (IJAEA), 2026, pp. 79-82.

@article{svenhollemann2026,
  title   = {Low-Power FinFET 7nm VLSI Design for High-Speed SerDes Applications with PVT Variability Analysis and SRAM Static Noise Margin Optimisation},
  author  = {Sven Hollemann},
  journal = {International Journal of Advanced Engineering Application (IJAEA)},
  year    = {2026},
  pages   = {79-82},
  issn    = {3048-6807 (Online)},
  doi     = {10.5281/zenodo.19703422},
}

TY  - JOUR
AU  - Sven Hollemann
TI  - Low-Power FinFET 7nm VLSI Design for High-Speed SerDes Applications with PVT Variability Analysis and SRAM Static Noise Margin Optimisation
JO  - International Journal of Advanced Engineering Application (IJAEA)
PY  - 2026
SP  - 79-82
SN  - 3048-6807 (Online)
DO  - 10.5281/zenodo.19703422
UR  - https://www.ijaea.com/papers?paper=Low-Power+FinFET+7nm+VLSI+Design+for+High-Speed+SerDes+Applications+with+PVT+Variability+Analysis+and+SRAM+Static+Noise+Margin+Optimisation
ER  -